Cryptographic hardware acceleration
Cryptographic operations can be very expensive when performed in software. These operations can be performed by a hardware accelerator to improve performance. Cryptographic hardware acceleration is the use of hardware to perform cryptographic operations faster than they can be performed in software. Hardware accelerators are designed for computationally intensive software code.
Using software for Rivest-Shamir-Adelman (RSA) operations (which are commonly used in public key cryptography) limits the number of operations that can be performed to the tens-per second-range. Hardware acceleration allows a system to perform up to several thousand RSA operations per second.
The CP Assist for Cryptographic Function (CPACF) is a coprocessor that uses the DES, TDES, AES-128, AES-256, SHA-1, SHA-256, and SHA-512 ciphers to perform symmetric key encryption and calculate message digests in hardware.